1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to an automated method of controlling critical dimensions of features by controlling the exposure dose of an exposure process performed in a stepper tool, and system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11, such as doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped-polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modem semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor processing involves the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and selectively removing portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., must be formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modem devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.2 xcexcm (2000 xc3x85), and further reductions are planned in the future. In general, the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Moreover, it is also desirable that manufacturing operations produce such features in a consistent, reliable and predictable manner. That is, it is desirable that features be formed in a manner such that there is little variation in final feature sizes, despite forming millions of such features on different substrates using different process tools to form such features.
In modem semiconductor fabrication facilities, a variety of factors may tend to cause variations in the size of fabricated structures or features, as compared to the intended or design size of those features. For example, photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above a layer of material that is desired to be patterned using the patterned photoresist layer as a mask. In general, in photolithography operations, the pattern desired to be formed on the underlying layer of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist reflecting the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer.
However, for a variety of reasons, the photolithography process often introduces some errors between the size of the image or feature as formed on the reticle, and the resulting image or feature as formed in the patterned layer of photoresist. Such errors may be due to a variety of factors, such as degradation or damage to the light source of the stepper tool, the positioning of the layer of photoresist relative to a light source, lens degradation or tool vibration, etc. Such factors may lead to the formation of a patterned layer of photoresist in which the critical dimensions of the feature in the patterned layer of photoresist are less than or greater than a desired target value. As a result of such variations, features may be formed in the underlying layer of material that have critical dimensions that are greater than or less than the desired feature sizes. Moreover, such variations may also be different depending upon which stepper tool is used in the process.
Variations in etching processes and equipment may also cause variations in the critical dimension of features on integrated circuit devices. For example, due to a variety of factors, an etching tool, or type of etching tool, may not etch the underlying process layer exactly in correspondence with the patterned layer of photoresist formed thereabove. That is, the etching process may result in the underlying feature in the process layer having a critical dimension that is greater than or less than the critical dimension of the feature formed in the patterned layer of photoresist. Such variations may result from a variety of factors, e.g., the cleanliness of the etching tool, any recent maintenance procedures performed on the tool, defective tool performance, variations in process recipe or constituent gases, etc.
Given the continual reduction of feature sizes in modern integrated circuit devices, it continues to be very important that feature sizes be defined as accurately as possible, and that such processes be repeatable. Thus, a need exists for a method and system that allows for automated control of the formation of critical feature dimensions in modern integrated circuit devices. The present invention is directed to a method and system that solves, or reduces, some or all of the aforementioned problems.
The present invention is directed to an automated method of controlling critical dimensions of features by controlling the stepper exposure dose, and a system for accomplishing same. In general, the present invention involves measuring a critical dimension of a plurality of features formed in a process layer (FICD dimension) and/or measuring a critical dimension of a plurality of features formed in a patterned layer of photoresist (DICD dimension) and using, individually or collectively, the FICD dimensions and the DICD dimensions to determine an exposure dose of an exposure process to be performed by a stepper tool or subsequently processed wafers.
In one illustrative embodiment, the method comprises measuring a critical dimension of a plurality of features formed in a process layer formed on a wafer, providing the measured critical dimensions of the features in the process layer to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer, forming a layer of photoresist above a process layer formed above said subsequently processed wafer, and performing the exposure process on the layer of photoresist on the subsequently processed wafer using the determined exposure dose.
In another illustrative embodiment, the method comprises measuring a critical dimension of a plurality of features formed in a patterned layer of photoresist that is formed above a process layer formed on a wafer, providing the measured critical dimensions of the features in the patterned layer of photoresist to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer, forming a layer of photoresist above a process layer formed above a subsequently processed wafer, and performing the exposure process on the layer of photoresist on the subsequently processed wafer using the determined exposure dose.
In yet another illustrative embodiment, the method comprises measuring a critical dimension of a plurality of features formed in a patterned layer of photoresist that is formed above a process layer formed on a wafer, measuring a critical dimension of a plurality of features formed in a process layer formed on a wafer, providing the measured critical dimensions of the features in the patterned layer of photoresist and the features in the process layer to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer, forming a layer of photoresist above a process layer formed above a subsequently processed wafer, and performing the exposure process on the layer of photoresist on the subsequently processed wafer using the determined exposure dose.
In one illustrative embodiment, the system disclosed herein comprises a metrology tool for determining a critical dimension of a plurality of features 23A, 27A formed in a process layer 23 formed on a wafer, a controller that determines, based upon the measured critical dimensions of the features, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer, and a stepper tool that performs the exposure process on the at least one subsequently processed wafer using the determined exposure dose. In another embodiment, critical dimensions of a plurality of features 25A, 27 formed in a patterned layer of photoresist are provided to the controller 38, and those critical dimensions, alone or in addition to the critical dimensions of the process layer, are used to determine the exposure dose on subsequent wafers.